(1) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a large capacity NAND type mask ROM having a memory cell gate length of one half micron or below.
(2) Description of the Related Art
A prior art method for fabricating a NAND type mask ROM of the kind to which the present invention relates is first explained with reference to FIGS. 1A to 1C. As shown in FIG. 1A, on a P-type silicon substrate 1, a field oxide film 2 is formed by using a selective oxidization process. By the field oxide film 2, the substrate 1 is divided into a memory cell region 3 and a peripheral transistor region 4. A gate oxide film 5 is then formed, and then gate electrodes 6a to 6e having a polysilicon or polycide structure are formed. Then, N.sup.- -type diffusion layers 7a to 7g are formed by ion implantation with the gate electrodes 6a to 6e used as masks. Then, as shown in FIG. 1B, an insulating film 8 is deposited over the entire surface of the P-type silicon substrate 1. The insulating film 8 is deposited such that it has a substantially uniform thickness on the entire surface of the gate electrodes 6a to 6e.
Then, as shown in FIG. 1C, the entire surface of the insulating film 8 is etched-back by anisotropic dry etching to form side walls 9a to 9j of insulating film 8. Then, N.sup.+ -type diffusion layers 10a to 10g are formed by ion implantation with the gate electrodes 6a to 6e and side walls 9a to 9j used as masks. Thus, N-channel LDD transistors 11a to 11e are formed in the memory cell region 3 and peripheral transistor region 4, thus completing a base structure of NAND type mask ROM. Where a CMOS circuit (not shown) is adopted, P-channel transistors are formed in the peripheral transistor region 4. Subsequently, data writing is performed by changing the desired transistors in the memory cell region 3 from enhancement type to depletion type by ion implantation. After a subsequent interconnection step, the NAND type mask ROM is completed.
With recent NAND type mask ROM integration density increase, each of the inter-gate electrode intervals between adjacent ones of the gate electrodes 6a to 6d in the memory cell region 3 is reduced to be one half micron or below. Since the side walls 9a to 9h are formed in such narrow spaces, the ion implantation is made incompletely. Therefore, the N.sup.+ -type diffusion layers 10b to 10d are formed such that they have less junction depth compared to the N.sup.+ -type junction layers 10a and 10e to 10g or, in an extreme case, fail to be formed. A problem that occurs in this connection is a decrease of "on" current in the N-channel enhancement type transistors 11a to 11d, which results in a lowering of the reliability and yield of the device.